1) Field
Embodiments of the present invention pertain to the field of Integrated Circuit (IC) Device Processing and, in particular, to self-aligned double patterning (SADP) of an IC device.
2) Description of Related Art
In a conventional semiconductor lithographic process a mask or reticle is positioned above a photoresist layer during a lithographic process exposing the layer to radiation (hv) having a particular wavelength (λ). Each feature of patterned photoresist layer has a critical dimension (CD) and is adjacent to another patterned feature spaced apart by a distance. The feature CD added to the space between features is typically referred to as the pitch.
The resolution limit for a particular lithographic process may be characterized with features having a CD equal to the space between the features. For example, a conventional 193 nm lithography system may provide a minimum pitch of 130 nm and a 65 nm half pitch. To reduce the effective half pitch of patterns formed in a substrate, density-sensitive integrated circuit (IC) product lines, such as dynamic random access memory (DRAM), are pursuing double patterning (DP) to define a pattern in a substrate having a half pitch below that lithographically achievable with the particular lithography employed (e.g., “sub-minimum half-pitch”). One type of DP is known as self-aligned DP (SADP) where a sidewall spacer mask is fabricated having spacer lines formed adjacent to the sidewalls of a template mask. For every line of the template mask, two spacer mask lines are generated. As such, a spacer mask providing substantially the same critical dimension (or less) for each line, but having double the density of lines in a particular region, may be fabricated.
Because SADP methods are independent of the lithographic technology employed, they can be practiced with 193 nm lithography as well as high NA or EUV lithography to provide a sub-minimum half pitch. SADP methods however are potentially cost prohibitive, particularly as a result of production cycle time, which increases when a DP method employs many additional operations to pattern a particular layer. Furthermore, SADP methods pose a difficulty where pitch reduction is desired in only one portion of an IC, such as a memory cell area, while no reduction in pitch from a lithographically defined mask pattern is desired in another portion of the IC, such as a periphery area. SADP methods requiring a lithographic patterning of a cell area separate from a periphery area are disadvantageous in that a particular device layer would then require two separate masks and lithography operations (i.e., a first mask to pattern regions not employing SADP and a second mask to pattern regions with a SADP process).